Semiconductor storage apparatus

ABSTRACT

A semiconductor integrated circuit includes first to eighth column selection transistors and ninth to twelfth column selection transistors. The ninth column selection transistor is connected to the first and second column selection transistors. The tenth column selection transistor is connected to the third and fourth column selection transistors. The eleventh column selection transistor is connected to the fifth and sixth column selection transistors. The twelfth column selection transistor is connected to the seventh and eighth column selection transistors. A first column selection line is connected to gates of the first, third, fifth and seventh column selection transistors. A second column selection line is connected to gates of the second, fourth, sixth and eighth column selection transistors. Third to sixth column selection lines are connected to gates of the ninth to twelfth column selection transistors, respectively.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of Ser. No. 10/052,303 filed Jan. 18,2002 now U.S. Pat. No. 6,552,936.

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2001-010242, filed Jan. 18,2001, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data reading technique of asemiconductor storage apparatus, particularly to a fast data readingtechnique.

2. Description of the Related Art

When a semiconductor storage apparatus (e.g., NOR type flash memory) isaccessed at random, a series of reading operation including: selecting acell for each address input; sensing cell data; and outputting the datais repeated. Therefore, a certain given time is required, and the datacannot be outputted faster.

On the other hand, a serial access operation includes: selecting cellscorresponding to a plurality of addresses present on the same word lineat the same time; sensing the data; latching the sensed data; andsequential outputting the latched data in synchronization with a clockfrom the outside. Therefore, a fast data reading is apparently realized.

Furthermore, when the latched data is sequential outputted, a next groupof cells are sensed in a chip. Since a so-called “pipeline reading” isperformed, an internal reading delay can be eliminated in and after afirst access, and the fast data reading is enabled.

The “pipeline reading” has heretofore been realized by dividing a memorycell array into two, and disposing a decoder and sense amplifier in thetwo arrays, respectively. Therefore, a chip area has largely increased.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to an aspect of the inventioncomprises: first to eighth bit lines; a plurality of memory cells beingconnected to the first to eighth bit lines; first to eighth columnselection transistors, one of a source and drain of each of the first toeighth column selection transistors being connected to a correspondingone of the first to eighth bit lines; ninth to twelfth column selectiontransistors, one of a source and drain of the ninth column selectiontransistor being connected to the other of the source and drain of eachof the first and second column selection transistors, one of a sourceand drain of the tenth column selection transistor being connected tothe other of the source and drain of each of the third and fourth columnselection transistors, one of a source and drain of the eleventh columnselection transistor being connected to the other of the source anddrain of each of the fifth and sixth column selection transistors, oneof a source and drain of the twelfth column selection transistor beingconnected to the other of the source and drain of each of the seventhand eighth column selection transistors; first and second senseamplifiers, the first sense amplifier being connected to the other ofthe source and drain of each of the ninth and tenth column selectiontransistors, and the second sense amplifier being connected to the otherof the source and drain of each of the eleventh and twelfth columnselection transistors; a first column selection line being connected togates of the first, third, fifth and seventh column selectiontransistors; a second column selection line being connected to gates ofthe second, fourth, sixth and eighth column selection transistors; andthird to sixth column lines being connected to gates of the ninth totwelfth column selection transistors, respectively.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a circuit diagram showing one example of an NOR type flashmemory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an access order of a circulatory interleaveaccess.

FIG. 3 is a diagram showing an access order of a circulatory continuousaccess.

FIG. 4 is a circuit diagram showing one example of a column gate drivingcircuit 6.

FIG. 5 is a diagram showing a truth value when a signal INTERLEAVE is“LOW”.

FIG. 6 is an operation timing chart showing a circulatory interleaveaccess operation (pipeline reading).

FIG. 7 is a circuit diagram showing one example of an address controlcircuit with respect to a circulatory serial access.

FIG. 8 is a circuit diagram showing one example of an output multiplexcontrol circuit for a circulatory interleave access.

FIG. 9 is a circuit diagram showing one example of the output multiplexcontrol circuit for a circulatory continuous access.

FIG. 10 is a diagram showing a combination simultaneously selected bythe circulatory continuous access.

FIG. 11 is an operation timing chart showing a circulatory continuousaccess operation (pipeline reading).

FIG. 12 is a circuit diagram showing one example of the NOR type flashmemory according to a third embodiment of the present invention.

FIG. 13 is a diagram showing an access order of a non-circulatorycontinuous access.

FIG. 14A is a diagram showing one example of the address control circuitwith respect to a non-circulatory serial access, and FIG. 14B is acircuit diagram showing one circuit example of a circuit block 100 shownin FIG. 14A.

FIG. 15 is a circuit diagram showing one example of an output multiplexcontrol circuit for the non-circulatory continuous access.

FIG. 16 is an operation timing chart showing a non-circulatorycontinuous access operation (pipeline reading).

FIG. 17 is a circuit diagram showing one example of the NOR type flashmemory according to a fourth embodiment of the present invention.

FIG. 18 is a circuit diagram showing one example of an outputmultiplexer having a replacement function.

FIG. 19 is a circuit diagram showing one example of the NOR type flashmemory according to a fifth embodiment of the present invention.

FIG. 20 is a circuit diagram showing one example of a data latch havinga replacement function.

FIG. 21 is a circuit diagram showing one example of the NOR type flashmemory according to a sixth embodiment of the present invention.

FIG. 22 is a block diagram showing one modification example according toa sixth embodiment of the present invention.

FIG. 23 is a circuit diagram showing one example of a data readingsystem circuit of the NOR type flash memory according to a seventhembodiment of the present invention.

FIG. 24 is an operation timing chart showing a data output timingaccording to a seventh embodiment.

FIG. 25 is an operation timing chart showing the data output timingaccording to an eighth embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described hereinafter withreference to the drawings. For the description, common parts in all thedrawings are denoted with common reference numerals.

First Embodiment

Constitutions of a memory cell array, column gate, and sense amplifierwill first be described with reference to FIG. 1 in terms of an exampleof an NOR type flash memory.

FIG. 1 is a circuit diagram showing one example of the NOR type flashmemory according to a first embodiment of the present invention.

As shown in FIG. 1, word lines (WL0 to WL2) of a memory cell array 1arranged in an NOR type are selected via a row decoder 2 which receivesa row address. A bit line is selected, when a tree-shaped transmissiongate (column gate) 3 is opened and connected to sense amplifiers (S/A)4.

In one example shown in FIG. 1, the column gate 3 has a tree structureof two stages, and one column gate line is selected by a column gatedriving circuit (Col. Gate Driver) 5 which receives corresponding columnaddresses (COL_0 to COL_2) and column gate driving circuit (Col. GateDriver) 6 which receives a column address (COL_3). In this case, aplurality of addresses of cells, for example, cells designated by fouraddresses are simultaneously selected, and sensed, and data is held in adata latch 7. For the latched data, an output multiplexer 9 selects thedata corresponding to addresses sequential selected by an addresscontrol circuit (Address Controller) 8 and outputs the data to an outputbus.

In FIG. 1, one I/O is noted. In actual, the same circuit exists for therespective I/Os.

As a major characteristic of the present embodiment, three addresssignals COL_0 to COL_2 are inputted into the column gate driving circuit6, so that eight column gates CG2_0 to CG2_7 can individually andindependently selected.

There are several types of an access order of the serial access, and twotypes of circulatory serial access of eight addresses are shown in FIGS.2, 3.

FIG. 2 is a diagram showing the access order of a circulatory interleaveaccess in the serial access, and FIG. 3 is a diagram showing the accessorder of a circulatory continuous access in the serial access.

In the interleave access shown in FIG. 2, a first combination of fouraddresses is only (0,1,2,3) or (4,5,6,7).

On the other hand, in the continuous access shown in FIG. 3, there arecombinations for a top address, that is, eight combinations.

In one circuit example shown in FIG. 1, since eight column gates CG2_0to CG2_7 are independently drive, four arbitrary column gates CG2 cansimultaneously be opened.

One example of the column gate driving circuit 6 which realizes both theinterleave access shown in FIG. 2 and the continuous access shown inFIG. 3 is shown in FIG. 4.

As shown in FIG. 4, when a signal INTERLEAVE is “HIGH”, the selectedcolumn is determined only by COL_2. When COL_2=“LOW”, the column gatesCG2_0, CG2_2, CG2_4, CG2_6 are selected. When COL_2=“HIGH”, the columngates CG2_1, CG2_3, CG2_5, CG2_7 are selected. In these cases, thememory cells corresponding to the addresses (0,1,2,3) and (4,5,6,7) areaccessed.

Moreover, a truth value table of a time when the signal INTERLEAVE is“LOW” is shown in FIG. 5.

An interleave access operation will next be described in more detail.

FIG. 6 is an operation timing chart showing an interleave pipelinereading operation.

As shown in FIG. 6, when the latched data for four addresses (A0, B0,C0, D0 in this example) are sequential outputted, the cells for the nextfour addresses are selected and sensed (pipeline-operated), andtherefore an internal delay of a sensing time cannot be seen outside achip.

Read data (Dataout) is sequential outputted in a predetermined addressorder in synchronization with a clock signal inputted via CLKPAD.

First, a reading start address inputted into an address pad is latchedat a first rising of CLK, after a chip enable signal/CE=“LOW”. A bias isapplied to the word line (WL0) and column gates (CG1_0 to CG2_0) inaccordance with the latched address, and sensing is started with respectto respective bit lines of A0, B0, C0, D0. When the data for fouraddresses is latched in the data latch 7 shown in FIG. 1, data output isstarted.

In the present example, simultaneously with the start of the dataoutput, COL_2 is reversed, the selected column gate is switched toCG2_1, and respective bit lines of A1, B1, C1, D1 are sensed. Thesensing is ended, and latched data is updated, before D0 is outputted asthe read data. Then, data of A1 can be outputted continuously after thedata of D0.

One example of the address control circuit 8 for realizing thisoperation is shown in FIG. 7, and one example of an output multiplexcontrol circuit is shown in FIG. 8.

In the address control circuit 8 shown in FIG. 7, and the outputmultiplex control circuit shown in FIG. 8, the address is first latched,and only COL_2 is reversed after four clocks. This can realize theoperation shown in FIG. 6.

Moreover, in FIGS. 6 to 8, a simple case of 1 clock 1 data out isassumed. With a relation between a clock frequency and the internalsensing time, for example, in 2 clocks 1 data out, after eight clocksare counted, COL_2 may be reversed.

Second Embodiment

In the first embodiment, the circulatory interleave access has mainlybeen described. In a second embodiment, an example of circulatorycontinuous access is shown.

The continuous access shown in FIG. 3 is realized by modifying theoutput multiplex control circuit of the constitution shown in FIG. 1 asshown in FIG. 9.

A characteristic of the circulatory continuous access lies in that thecombination of simultaneously selected cells changes with a startaddress. Concretely, it is necessary to simultaneously select the cellsas shown in FIG. 10. When the constitution of the column gate 3 shown inFIG. 1 is used, and the signal of the column gate driving circuit 6shown in FIG. 4 is set to INTERLEAVE=“LOW”, the combination shown inFIG. 10 can be obtained.

In the cell constitution shown in FIG. 1, four bit lines are allotted toone sense amplifier. To select one bit line in accordance with theaddress signal, the address signal of two bits is essentiallysufficient.

However, COL_1, COL_0 used in the multiplexer of a sense amplifieroutput are also inputted to the column gate driving circuit 6 of CG2,and a column gate signal of CG2 is all divided for every four senseamplifiers.

In this case, the cells for four arbitrarily continuous addresses can beselected from the cells for eight addresses (COL_2,COL_1,COL_0)=(0,0,0)to (1,1,1). In the column gate driving circuit 6 for driving CG2 shownin FIG. 4, when the signal INTERLEAVE=“LOW”, the simultaneous selectionshown in FIG. 10 is enabled in accordance with the start address.

When the start address is (0,0,0)=0, the cells of addresses 0 to 3 areobediently selected. Moreover, for example, with the start address(0,0,0)=1, CG2_1,2,4,6 (not CG2_0 but CG2_1) are opened, and therebyfour address cells for continuous addresses 1 to 4 can be selected.After the cell data for four addresses is latched in the data latch(data latch 7 shown in FIG. 1), COL_2 is reversed. Then, CG2_0,3,5,7 areselected and cells of addresses 0,5,6,7 are read.

After the cells for four addresses are sensed, COL_2 is reversed, andthereby the remaining cells for four addresses are simultaneouslyselected.

A timing of the circulatory continuous access operation (pipelinereading) using the aforementioned constitution is shown in FIG. 11. Acontrol method of the address is the same as that of the firstembodiment, and the address control circuit 8 shown in FIG. 7 may beused.

In FIG. 11, the column gate CG2_0 is selected again. After D1 isoutputted, the data returns to A0, and is circulated and outputted. Itis possible to easily perform a control for outputting the cells foreight addresses only once and stopping data output (Data Out).

Additionally, the access of the first embodiment is different from theaccess of the second embodiment only in the output multiplex control.Therefore, when the output of the output multiplex control circuit isswitched, either access can be realized on the same chip. To change anoutput order, a fuse for use in R/D replacement or a command inputtedfrom the outside of the chip may be used.

Furthermore, when a logic of the output multiplex control circuit shownin FIG. 9 is combined with a logic of the output multiplex controlcircuit shown in FIG. 8, the circulatory continuous access shown in FIG.3 and the circulatory interleave access shown in FIG. 2 can be realizedon the same chip. Concretely, for example, an exclusive NOR 21 in FIG. 8is connected in parallel to an adder 22 in FIG. 9, the signal INTERLEAVEfor switching the interleave access and continuous access is used, andeither one of the exclusive NOR 21 and the adder 22 may be set to beactive.

Moreover, both in the first and second embodiments, the pipelineoperation for sequential sensing the cells for four addresses has beendescribed as an example. For example, when eight addresses aresimultaneously sensed, the serial access of 16 addresses can berealized.

Third Embodiment

The first and second embodiments show the example relating to thecirculatory serial access. A third embodiment shows an example relatingto a non-circulatory serial access, for example, a serial access inwhich the addresses sequential increase.

One example of an NOR type flash memory according to the thirdembodiment of the present invention is shown in FIG. 12, and the accessorder of a non-circulatory continuous access is shown in FIG. 13.

With the non-circulatory continuous access, it is necessary to count upthe address. One example of the address control circuit 8 which cancount-up the address is shown in FIG. 14A. Moreover, FIG. 14B shows onecircuit example of a circuit block 100 shown in FIG. 14A.

The address control circuit 8 shown in FIG. 14A sequential counts uphigh-level addresses every four clocks from COL_2.

On the other hand, as shown in FIG. 15, for an output multiplex controlcircuit in which COL_0, COL_1 are used to sequential serially outputpredetermined data from the data latch 7 in synchronization with theclock, a circuit substantially equal to the output multiplex controlcircuit shown in FIG. 9 can be used.

However, with a start address other than (COL_2,COL_1,COL_0)=(0,0,0),(1,0,0), the output of the pipeline reading is not in time with fourclocks in some case. For example, assume that the start address is(1,0,1), that is, address 5. In the first sensing after the start ofreading, the cells of addresses 5,6,7,0 (B1,C1,D1,A0) are selected andsimultaneously sensed. While the data are outputted, the cells for thenext four addresses are sensed. Although the data for four addresses5,6,7,8 (B1,C1,D1,A2) originally have to be outputted, the cell ofaddress 8 (A2) is not selected. To select this cell, the gate of CG1 hasto be switched.

Therefore, after the cell data of address 7 is outputted, it isnecessary to stop the count up in the output multiplex control circuitshown in FIG. 15. Therefore, in the output multiplex control circuit ofFIG. 15, when address (OUT_1,OUT_0) of output data selection turns to(1,1) before counting four clocks, the count-up is controlled anddiscontinued.

FIG. 16 is an operation timing chart showing a non-circulatorycontinuous access operation (pipeline reading).

As shown in FIG. 16, with the non-circulatory continuous access, whilefirst eight addresses are read, with a low-level start address otherthan 0, three clocks at maximum are waited for. Thereafter, the addresscan continuously be read without delay until the row address isswitched.

Of course, when the column gate CG1 is independently controlled likeCG2, the continuous serial access can be realized without delay withrespect to changing of the column. However, the same number of columngates as the number of bit lines exist in CG1, and an area penalty islarge in independently controlling the respective column gates. It ispreferable to perform the independent control of the column gates in thehigh-level of a tree.

Fourth Embodiment

A fourth embodiment is an example in which a redundancy technique isapplied to the present invention.

In a semiconductor storage apparatus, when defective memory cellsgenerated by a processing defect are replaced with spare columns (bitlines), a product defect is prevented. A redundancy system will bedescribed which includes: also reading the cell data of the sparecolumns at the same time during reading; judging whether the column tobe replaced is included in the accessed address; and changing the senseamplifier output.

FIG. 17 is a circuit diagram showing one example of the NOR type flashmemory according to the fourth embodiment of the present invention, andshows a constitution in which the serial access is realized with respectto the memory cell array including redundant columns (spare columns).

As shown in FIG. 17, in the fourth embodiment, in addition to theconstitution of FIG. 1, S/A 4RD for the redundant columns, and datalatch 7RD for the redundant columns are disposed, and redundant cells(spare cells) are sensed together with main cells during sensing.Moreover, at a time of data output, the input address is compared withFuse data for defective address information. At a time of hit(agreement), the data sensed by the S/A 4RD for the redundant columnsand latched by the data latch 7RD for the redundant columns replaces thedata corresponding to a defective address in the data latch 7 by anoutput multiplexer 9′, and instead the data latch 7RD for the redundantcolumns is selected. In the present description, the output multiplexer9′ is referred to as a multiplexer with a replacement function. Theredundant column is accessed every address, the sense amplifier outputis multiplexed at a data output stage, and thereby a time for judgingspare replacement can apparently be eliminated.

The column gate of the redundant column is controlled with the samesignal as the signal of a main body of the apparatus, or is constantlyopened. In FIG. 17, the same signal as that of the main body is used inCG1 on a cell side, and CG2_RD is constantly controlled to be “HIGH”.

Replacement with redundant column data in the multiplex at the dataoutput time will be described with reference to FIG. 18.

Upon receiving an input of internal addresses (high-level addresses fromCOL_2, COL_3), Fuse data is determined. In FIGS. 17, 18, signal HITRD isa signal for judging whether replacement is necessary, RDCOL_0, RDCOL_1are low-level addresses of replacement, and RDIO_0, RDIO_1, RDIO_2,RDIO_3 denote I/O of replacement. In this case, a data width is 16I/O.

When four address cells are selected by the internal addresses andsensed, Fuse data is simultaneously read, and latched by a column R/Dreplacement control circuit 10 of FIG. 18. At this time, since theaddress and I/O requiring the replacement are determined, defective dataoutput is disabled before the data output. When the replacement addressis hit with the serial access, a transmission gate is opened and R/Ddata is outputted.

Reading of the Fuse data may be ended during simultaneous sensing of thefour address cells.

In general, since the sensing time of the memory cell is longer, areading time of Fuse does not influence the access.

Fifth Embodiment

A fifth embodiment shows a second example in which the redundancytechnique is applied to the present invention.

FIG. 19 is a circuit diagram showing one example of the NOR type flashmemory according to the fifth embodiment of the present invention.

In the fourth embodiment, the sense amplifier 4RD connected to theredundant column also has the data latch 7RD, and performs the datareplacement in the multiplex of the data output time.

However, the data can also be replaced with the redundant cell data,when the data is held in the data latch 7. The constitution is shown inFIG. 19.

The output of the sense amplifier 4RD connected to the redundant columnis connected to all data latches 7′, and the data latch 7′ replaces theoutput of the sense amplifier 4 of the column corresponding to thedefective column address designated by Fuse, and latches the data. Inthe present description, the data latch 7′ is called a data latch with areplacement function. A concrete constitution of the data latch with thereplacement function 7′ and output multiplexer 9 is shown in FIG. 20.

In an example shown in FIG. 20, the defective cell data is alreadyreplaced with the redundant cell data, when the sensing and datalatching end. Therefore, as compared with the example shown in FIG. 18of the fourth embodiment, there can be obtained an advantage that it isunnecessary to latch the Fuse data (defective address, I/O data) in thecolumn R/D replacement control circuit 10.

Sixth Embodiment

A sixth embodiment shows an example in which the present invention isapplied to a technique for performing data reading and data writing ordata erasing in a dual manner.

FIG. 21 is a circuit diagram showing one example of the NOR type flashmemory according to the sixth embodiment of the present invention.

In the flash memory, the writing of the data into the cell, erasing, andverifying operation can automatically be controlled in the chip in somecase. The writing requires a time of several microseconds, and erasingrequires a time of several hundreds of milliseconds to several seconds,and the chip executing an automatic operation is usually in a busystate, and cannot be read or accessed. A read while write function (RWWfunction) for enabling the reading out to the cell other than the cellof the writing/erasing block even during execution of the automaticoperation is disposed can be realized by arranging two column gates CG2in parallel as shown in FIG. 21.

An RCG gate is a switch for connecting the bit line with the senseamplifier for reading, and has the same function as that of the firstembodiment. Gate ACG2 connected to the bit line in parallel to RCG2serves as a switch for connection to the sense amplifier for performingwriting/erasing verification during automatic operation.

IN FIG. 21, a plurality of sets of the memory cell array 1, row decoder2, column gate 3, column gate driving circuits 5, 6, 6′ are disposed inthe chip. The RWW function cannot be disposed among the cells by whichthe sets are shared. The RWW function can be realized only among thecells (banks) by which the word line, bit line, and driver circuit arenot shared. However, the address control circuit 8, sense amplifier 4,data latch 7, and output multiplexer 9 shown in FIG. 21 can be sharedand used.

For the RWW function, two sets of the address control circuit 8 andsense amplifier 4 are disposed for Auto and Read. The address controlcircuit for Read controls the address and clock for the reading.

On the other hand, in the address control circuit for Auto, the addresswritten from the outside of the chip, or deleted/designated by a commandis latched until the automatic operation ends.

For the addresses to be inputted to the row decoder 2, column gatedriving circuits 5, 6, 6′, it is judged whether the memory cell array 1as an object is during Auto or Read, and the corresponding address isdesignated by an address selector 11, and inputted. For the column gatedriving circuits 6, 6′, with the address for Auto, only the column gatedriving circuit 6′ is activated for connection to a sense amplifier 4′for Auto, and the column gates of RCG2 are all closed. This is totallyreverse to the operation of a Read time.

In the present embodiment, the sense amplifier is divided into the senseamplifier 4 for Read and sense amplifier 4′ for Auto. Thereby, the senseamplifier 4 for Read is disposed for “4×data width”, and the senseamplifier 4′ for Auto is disposed for “1×data width”.

If the sense amplifier 4 is shared for the reading and verifying and theRWW function is to be realized, the sense amplifiers for 4×16=64+R/Dwith four addresses and data width of 16 are required every unit (bank)of RWW. For example, in a two-banks constitution, 128 sense amplifiersare necessary.

On the other hand, when the function of the sense amplifier 4 is dividedfor the reading and verifying, the number of sense amplifiers for theverifying can be reduced, for example, to 16 amplifiers for one word. Inthis example, there are provided the reading sense amplifier 4 and theverifying sense amplifier 4′.

Moreover, when a writing load transistor for writing a hot electron isconnected only to the verifying sense amplifier 4′, a load capacity ofthe bit line for the reading can be reduced, and the sensing time caneffectively be reduced.

Furthermore, the reading sense amplifier 4 and verifying sense amplifier4′ can also be shared by at least two memory cell arrays which do notshare the decoder. A concrete example is shown in FIG. 22.

As shown in FIG. 22, the reading sense amplifier (READ S/A) 4 is sharedby a memory cell array (MEMORY CELL ARRAY A) 1A and memory cell array(MEMORY CELL ARRAY B) 1B, and the verifying sense amplifier (VERY. S/A)4′ is similarly shared by the memory cell array 1A and memory cell array1B.

The row of the memory cell array 1A is selected by a row decoder (RowDEC. A) 2A, and the row of the memory cell array 1B is selected by a rowdecoder (Row DEC. B) 2B. Similarly, the column of the memory cell array1A is selected by a column gate (Col. GATE A) 3A, and column gatedriving circuits (Col. GATE DRV. A) 5A, 6A, 6′A, and the column of thememory cell array 1B is selected by a column gate (Col. GATE B) 3B, andcolumn gate driving circuits (Col. GATE DRV. B) SB, 6B, 6′B. The memorycell arrays 1A and 1B do not share the decoder in this manner.

In an example of FIG. 22, since the reading sense amplifier 4 andverifying sense amplifier 4′ are shared by the memory cell arrays 1A and1B, the chip area can be inhibited from increasing.

Seventh Embodiment

In a synchronous reading operation, the data has to be outputted insynchronization with an external clock. During the reading operation,timings of the word line to the selected memory cell, bit line bias,sense amplifier enable, sense output latch, and the like are necessary,and these timings can also be prepared from an external clock.

However, an external clock frequency fluctuates with a system in whichthe chip is mounted, and is not constant. An upper limit of thefrequency is determined by a value which can continuously be outputtedwithout delay in a pipeline operation. For a lower limit, a frequencyrange has to be expanded without any principle. During reading of a slowperiod, when the timing is prepared by the external clock, undesirableproblems such as a wastefully long-time biased cell are generated inreliability.

To solve the problem, only the timings of the latch of the senseamplifier output, output of the latched data, and access start to thenext address are synchronized with the external clock. For internaltimings of equalizing and precharging of a sense line and referenceline, sense amplifier enable, and the like, it is considered to generatethe timings with an internal delay as in a conventional art. Then, thebias onto the cell and the sense timing do not depend on the frequencyof the external clock, and further matching with a conventional asynchronous operation is facilitated.

An inverter array circuit for opening/closing a path extending throughthe sense amplifier 4, data latch 7, output multiplexer 9, and dataoutput according to a seventh embodiment of the present invention isshown in FIG. 23.

As shown in FIG. 23, an output SAOUT of the sense amplifier 4 istransferred to and latched by a data latch 17, when a signal SALATB is“HIGH”. For the latched data, low-level column addresses (COL_0, COL_1)are received at a timing of SELDATA=“HIGH”, one piece of data isselected from a plurality of pieces of data, outputted to DATABUS, andlatched by a latch a (function of an output multiplexer 19).

With the synchronous serial access, the next coming data is known.Therefore, while the data is outputted to the outside of the chip, thenext data is brought to the latch a. A signal LATB is raised at a timingCLKPAD and immediately new data can be outputted.

A timing chart of the timings of the respective signals is shown in FIG.24.

It is assumed that CEBPAD=“LOW”, and the input address is latched at afirst rising of CLKPAD. A signal INITIAL is an initializing signal of areading circuit, used in discharging electricity from the sense lineconnected to the sense amplifier, starting an operation of a constantcurrent source of a differential amplifier, and the like, and can beassociated with an a synchronous address transition detect signal ATD.To access and sense the cell, an a synchronous internal delay circuit isused. The bit line is precharged in response to a signal PRE, and thesensing starts, when a signal “SENSE” is “HIGH”.

An operation for transferring the sense amplifier output SAOUT to thedata latch 17 and selecting the output by the multiplexer 19 isperformed in synchronization with the clock signal inputted via CLKPAD.These signals are SALATB, SELDATA, LATB. At a first access time,SALATB=“HIGH”, and the sense amplifier output SAOUT is transferred tothe data latch 17 as it is. Subsequently, after CEBPAD=“LOW” and apredetermined number of clocks, with transition to SALATB=L, the datafor four addresses is fixed. The fixed number of clocks constituteLATENCY of the first access, and a minimum LATENCY clock number changeswith an internal reading rate and clock frequency.

Thereafter, SALATB opens a transfer gate every four clocks, and takes inSAOUT for new four addresses. The high-level address is counted up fromCOL_2 at a falling of SALATB, and the reading for the next fouraddresses starts. After SALATB=L, the signal INITIAL is “HIGH” till therising of the first clock. Thereafter, similarly as the first access,the timings of PRE, SEN by the internal delay are generated.

An operation (LATB) for selecting (SELDATA) one piece of data from thefour addresses data, and outputting the data to an I/O pad from anoutput buffer is performed every clock. The data transferred to DATABUSat a timing of SELDATA is first latched by the latch a of FIG. 23.Moreover, with LATB=“HIGH”, the data is actually transferred to theoutput buffer, and with LATB=“LOW”, the transfer gate is closed. Then,with SELDATA=“HIGH”, the next data is outputted to the latch a.

Eighth Embodiment

For the timing of the seventh embodiment shown in FIG. 24, the timing(SELDATA) of the output multiplexer for selecting the output data fromthe data latch 17 is a basic clock of the synchronous operation. Bothtimings of rising and falling of the input clock from a clock pad areused to control the operation. In a CMOS gate logic, the rising of logicdepends on a driving ability of pMOS, and the falling depends on adriving ability of nMOS. Therefore, when a balance of the drivingability of the transistor collapses in a process condition, a differenceis generated in a rising delay and falling delay. In this case, in thetiming shown in FIG. 24, when the frequency of the basic clock israised, it is difficult to hold correlation and context of respectivecontrol signals.

On the other hand, as shown in FIG. 25, an eighth embodiment provides acontrol timing in which LATB is used as the basic clock of thesynchronous operation. In this case, except the first address latchtiming, only a falling edge of the clock input is used, and a controlsimply depending only on the clock frequency is performed.

According to the present invention described in the first to eighthembodiments, the memory cell on the same word line is sequentialselected only by switching the column gate, and the pipeline reading isrealized. As compared with the conventional art in which a decodercircuit is separated, the chip area can be reduced, and reading powerconsumption can be reduced.

Moreover, since the column gate signal is separately driven everyaddress in the simultaneous sensing of the plurality of addresses, thenumber of address-order outputs, double the number of sense amplifiers,can be outputted without delay.

Furthermore, the present invention is not limited to the first to eighthembodiments, and can variously be modified without departing from thescope of the present invention.

Additionally, the respective embodiments can of course be implementedalone or in an appropriately combined manner.

Moreover, the respective embodiments include various stages of thepresent invention, and various stages of the present invention can alsobe extracted by appropriately combining a plurality of constitutingelements disclosed in the respective embodiments.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventionconcept as defined by the appended claims and their equivalents what

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising: first to eighth bit lines; a plurality of memory cells beingconnected to the first to eighth bit lines, first to eighth columnselection transistors, one of a source and drain of each of the first toeighth column selection transistors being connected to a correspondingone of the first to eighth bit lines; ninth to twelfth column selectiontransistors, one of a source and drain of the ninth column selectiontransistor being connected to the other of the source and drain of eachof the first and second column selection transistors, one of a sourceand drain of the tenth column selection transistor being connected tothe other of the source and drain of each of the third and fourth columnselection transistors, one of a source and drain of the eleventh columnselection transistor being connected to the other of the source anddrain of each of the fifth and sixth column selection transistors, oneof a source and drain of the twelfth column selection transistor beingconnected to the other of the source and drain of each of the seventhand eighth column selection transistors; first and second senseamplifiers, the first sense amplifier being connected to the other ofthe source and drain of each of the ninth and tenth column selectiontransistors, and the second sense amplifier being connected to the otherof the source and drain of each of the eleventh and twelfth columnselection transistors, a first column selection line being connected togates of the first, third, fifth and seventh column selectiontransistors, a second column selection line being connected to gates ofthe second, fourth, sixth and eighth column selection transistors, andthird to sixth column selection lines being connected to gates of theninth to twelfth column selection transistors, respectively.
 2. Thedevice according to claim 1, further comprising: first and secondredundant bit lines; a plurality of memory cells being connected to thefirst and second redundant bit lines; first and second redundant columnselection transistors, one of a source and drain of each of the firstand second column selection transistors being connected to acorresponding one of the first and second redundant bit lines; a thirdredundant column selection transistor, one of a source and drain of thethird column selection transistor being connected to the other of eachof the first and second redundant column selection transistors; aredundant sense amplifier being connected to the other of the source anddrain of the third redundant column selection transistor; and aredundant column selection line being connected to a gate of the thirdredundant column selection transistor; wherein a gate of the firstredundant column selection transistor is connected to the first columnselection line, and a gate of the second redundant column selectiontransistor is connected to the second column selection line.
 3. Thedevice according to claim 2, wherein the plurality of memory cells arenon-volatile memory cells.
 4. The device according to claim 2, furthercomprising: a first selection transistor driving circuit being connectedto the first and second column selection lines, and a second selectiontransistor driving circuit being connected to the third to sixth columnselection lines, and wherein, the first column selection transistordriving circuit drives the first and second column selection lines inaccordance with a first address signal group; and the second columnselection transistor driving circuit drives the third to sixth columnselection lines in accordance with a second address signal group differfrom the first address signal group.
 5. The device according to claim 4,wherein the plurality of memory cells are non-volatile memory cells. 6.The device according to claim 4, wherein: the redundant column selectionline is connected to the second column selection transistor drivingcircuit; and the second column selection transistor driving circuitdrives the third to sixth column selection lines and the redundantcolumn line in accordance with the second address signal group.
 7. Thedevice according to claim 6, wherein the plurality of memory cells arenon-volatile memory cells.
 8. The device according to claim 1, furthercomprising: first to fourth write column selection transistors, one of asource and drain of the first write column selection transistor beingconnected to the other of each of the first and second column selectiontransistors, one of a source and drain of the second write columnselection transistor being connected to the other of each of the thirdand fourth column selection transistors, one of a source and drain ofthe third write column selection transistor being connected to the otherof each of the fifth and sixth column selection transistors, and one ofa source and drain of the fourth write column selection transistor beingconnected to the other of each of the seventh and eighth columnselection transistors, a verifying sense amplifier being connected tothe other of the source and drain of each of the first to fourth writecolumn selection transistors; and first to fourth column selection linesbeing connected to gates of the first to fourth write column selectiontransistors.
 9. The device according to claim 2, further comprising: afirst selection transistor driving circuit being connected to the firstand second column selection lines; and a second selection transistordriving circuit being connected to the third to sixth column selectionlines; and wherein: the first column selection transistor drivingcircuit drives the first and second column selection lines in accordancewith a first address signal group; and; the second column selectiontransistor driving circuit drives the third to sixth column selectionlines in accordance with a second address signal group differ from thefirst address signal group.
 10. The device according to claim 9,wherein: the first to fourth write column selection lines are connectedto the third column selection transistor driving circuit; and the thirdcolumn selection transistor driving circuit drives the first to fourthwrite column selection lines in accordance with a third address signalgroup differing from the first address signal group.
 11. The deviceaccording to claim 10, wherein the plurality of memory cells arenon-volatile memory cells.
 12. The device according to claim 9, whereinthe plurality of memory cells are non-volatile memory cells.
 13. Thedevice according to claim 8, wherein the plurality of memory cells arenon-volatile memory cells.
 14. The device according to claim 1, furthercomprising: a first selection transistor driving circuit being connectedto the first and second column selection lines; and a second selectiontransistor driving circuit being connected to the third to sixth columnselection lines, and wherein: the first column selection transistordriving circuit drives the first and second column selection lines inaccordance with a first address signal group; and the second columnselection transistor driving circuit drives the third to sixth columnselection lines in accordance with a second address signal group differfrom the first address signal group.
 15. The device according to claim14, wherein the plurality of memory cells are non-volatile memory cells.16. The device according to claim 1, wherein the plurality of memorycells are non-volatile memory cells.